Universal memory element with systems employing same and apparatus and method for reading, writing a

专利摘要:
The present invention relates to a general purpose memory element (302) having a multi-level, undetected state, a method and apparatus for programming it, and a neural network (32), methods and applications for embodying it in artificial intelligence and data storage systems. The general purpose memory element is insufficient to switch the memory element from a high resistance state to a low resistance state, but the accumulation of additional energy pulses may modify the memory material to switch the memory element from the high resistance state to the low resistance state And is programmed by applying one or more partial interval pulses sufficient.
公开号:KR20010052795A
申请号:KR1020007014103
申请日:2000-04-12
公开日:2001-06-25
发明作者:스탠포드 알. 오브신스키；보일 페시마코브
申请人:마빈 에스. 시스킨드；에너지 컨버젼 디바이시즈, 아이엔씨.；
IPC主号:

专利说明:

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a general-purpose memory element, a system using the general-purpose memory element, and an apparatus and a method for reading,
A general concept of using an electronically recordable and erasable phase change material (i.e., a material that can be electrically switched between a conventional amorphous state and a conventional crystalline state) for electrical memory applications is described, for example, U.S. Patent 3,271,591, issued to Ovshinsky on Sep. 6, 1996, assigned to the same assignee, and U.S. Patent No. 3,530,441, issued on Feb. 22, 1970, to Oshinsky, And these two disclosures are hereby incorporated herein by reference (hereinafter referred to as the " Oshinsky patent ").
As disclosed in the Ovshinki patent, such a phase change material can be varied between the conventional amorphous and the structural state of a conventional crystalline local order, or it can be varied between the complete amorphous state and the perfect crystalline state, Lt; RTI ID = 0.0 > a < / RTI > The initial material described by the Obsessian patent can be switched between two detectable structural states of conventional amorphous and conventional decision local orders to facilitate the storage and retrieval of a single bit of encoded binary information, These materials can be set as intermediate detectable levels of local order across the full spectrum between the fully amorphous state and the fully crystalline state.
That is, the Ovshinki patent does not require electrical conversion of such material to occur between a fully amorphous state and a fully crystalline state, but rather a detectable property such as a resistance, for example, between a fully amorphous state and a perfect crystalline state, And can be set as an arbitrary level over the order. This property of the varying local order provides a " gray scale " represented by the spectrum between the complete amorphous state and the perfect crystalline state. Such a gray scale characteristic can be used, for example, as a virtually infinite variable coefficient, such as a virtually infinite variable resistance between a maximum and a minimum level, or this characteristic can be used, for example, at a separately detectable step between the maximum and minimum levels Such as the resistance of the selected coefficient.
Variable coefficient characteristics, such as resistances that can be adjusted over the gray scale area, allow the application of such devices to neural networks and artificial intelligence systems, for example, as described in the Ovshinki patent. In other applications of such devices, such as those described in the Ovshinki patent, the use of factors for incrementing the coefficients and setting the individually detectable levels can lead to storage in a single memory element of multi-bit data.
Related Application Information
This application is a continuation-in-part of U.S. Serial No. 09 / 102,887 filed on June 23, 1998.
Field of invention
The present invention relates generally to programmable memory elements, and more particularly to erasable memory elements embodied in applications such as data storage, multi-value logic and neural network / artificial intelligence computing, Read, write and program the same. The memory element can be programmed by any one or more of the following energy input types: electrical, optical, pressure and / or thermal. In one embodiment, the information may be stored in the memory element of the present invention as an encrypted form that can only be retrieved by use of a specially programmed device and method. The present invention is therefore useful for storing information in an encrypted or secret format. In another embodiment, the invention is embodied in a neural network system.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a graphical illustration of a general purpose memory element of the present invention in which a device resistance is plotted on an ordinate and the amplitude of an applied current pulse is floated in abscissa, illustrating different programming schemes of the general purpose memory element.
2 is a flow diagram illustrating an embodiment of a method according to the present invention for writing data to a general purpose memory element of the present invention.
3 is a flow diagram illustrating an embodiment of a method according to the present invention for reading data from a general purpose memory element of the present invention.
4 is a flow diagram illustrating another embodiment of a method according to the present invention for reading data from a general purpose memory element of the present invention.
5 is a block diagram of an embodiment of an apparatus according to the present invention for writing and reading data from a general purpose memory element of the present invention.
6 is a cross-sectional view of a memory element of the present invention having first and second contacts each adjacent to a volume of memory material;
Figure 7 is a schematic metrics diagram of a portion of a neural processor embodying the present invention in which the general purpose memory elements of the present invention are combined.
FIG. 8 is a schematic view of a unit cell of a neural network structure according to the principles of the present invention; FIG.
9 is a schematic view of a portion of two stacked planes of a unit cell of a neural network structure according to the principles of the present invention.
10 is a schematic diagram of another embodiment of a unit cell of a neural network structure in accordance with the principles of the present invention, including a suppression line and a stimulation line.
11 is a schematic illustration of another unit cell of a neural network structure in accordance with the principles of the present invention, including a separate control line.
FIG. 12 is a schematic illustration of another unit cell of a neural network structure in accordance with the principles of the present invention, including a suppression line and a stimulation line controlled by a common input line; FIG.
Figure 13 is a plan view of a layout of multiple memory elements useful for data storage in accordance with the principles of the present invention, particularly how the elements are connected to a set of X-Y addressing lines.
14 is a schematic illustration of a matrix of memory elements useful for data storage in accordance with the principles of the present invention, and in particular how an isolation element, such as a diode, is electrically coupled to a memory element to electrically isolate each memory element from other elements. ≪ / RTI >
Figure 15 is a schematic diagram illustrating a single crystal semiconductor substrate having memory metrics integrated in accordance with the principles of the present invention in electrical communication with an integrated circuit chip to which an address driver / decoder is operatively attached.
16 is a schematic diagram of an embodiment of the present invention applied to control the connection capability between nodes of a node network in a neural network system;
Summary of the Invention
The present invention relates to a device that enables the formation of a general memory element that utilizes the characteristics of such phase change material that has been newly discovered and which has not been totally predicted and which utilizes such characteristics, and also relates to a method and apparatus for programming the memory element, Multi-valued logic and neural network / artificial intelligence systems that specify element devices.
In one implementation, such a universal memory element is used in a form and in a format in which information is stored by applying one or more sequential electrical pulses of a selected magnitude and duration to a memory element initially set to a high-resistance state. The selected magnitude and duration of each pulse is such that the application of an initial single pulse can not switch the memory element from its high resistance state to its low resistance state. However, the selected size and duration of each pulse is such that the individual pulses increase but cause a structural change in the memory element that can not be detected at this stage. These uniquely structured pulses are referred to herein as " sub-interval pulses " and are also referred to as " programming pulses " when applied to a predetermined write and / or read sequence. The characteristics of such partial interval pulses are discussed in greater detail in the following detailed description, but are briefly described below for a summary of the present invention.
What is noteworthy with regard to the instantaneous non-volatile general memory elements that are known in accordance with the present invention is that the set current pulses that set the memory element in its high resistance state to its low resistance state can be divided into sub- And the application of the individual fractional spacing pulses is such that the resistance of the memory device does not actually change until the total duration of the fractional spacing pulses is equal to or greater than the " set period " described above. When the last interspacing pulse carries the final increment of energy, the device is converted to a low resistance state.
Thus, the " set period " of the set current pulse may be divided into a desired number of sub-intervals. The number of partial intervals corresponds to the total number of multi-value-digital programming states of the element (in one embodiment the total number of programming states is one greater than the number of partial intervals). When a certain number of sub-interval current pulses are applied, the current state of the memory element is read by the application of an additional sub-interval programming pulse until the memory element is converted from its high-resistance state to its low-resistance state. By reading the resistance of the element between the individual partial interval pulses that are additionally applied, the number of additional pulses can be determined and can also be compared to the total number of programming states. This difference is the current state of the memory element. The fractional interval pulse is also referred to herein as " programming pulse ". In each case, the partial interval pulse or programming pulse is insufficient to change the phase change material, but switching the phase change material from the high resistance state to the low resistance state incrementally when combined with additional partial spacing or programming pulses Suffice.
The process of reading the current state of a memory element is "destructive reading" because it changes the current state. Therefore, it must be " reprogrammed " after the memory element is read. This is done by preferentially resetting the device to a high-resistance state by a high-amplitude current pulse referred to as a " reset current pulse ", and then applying a partial interval current pulse Apply the number. Thus, the information read from the memory element is restored when the element is reprogrammed.
In one embodiment, the general purpose memory element of the present invention is embodied in a data storage system in which multiple bits are stored in a respective single memory element. This greatly increases the storage density of the memory because multiple bits can be stored in each general purpose memory element. In this embodiment, the data is also stored in non-detectable form and such data can not be read or retrieved except by using the method and apparatus of the present invention as discussed in the following detailed description. Thus, this embodiment enables storage of information as a secret form that can not be completely detected by any means except for the apparatus and method of the present invention.
In another embodiment, the general purpose memory element of the present invention is embodied in a neural network and / or an artificial intelligence system that controls and forms between the nodes or between the row and column connections of the neural processor. In this second embodiment, a memory element coupled between the nodes or the row and column of the neural processor selects a selected number of partial interval pulses of the selected and assigned weight, e.g., a partial interval pulse, determined by programming and controlling the strategy of the neural network The memory element is switched to a low resistance state to provide maximum connection capability between the selected nodes or between rows and columns of the neural processor. The present embodiments will be further discussed in the following detailed description of the present invention.
These and various other embodiments and applications of the present invention and other important features and principles of the present invention will be discussed in the detailed description of the present invention.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a graph showing the amplitude of an applied current pulse versus device resistance for a general purpose memory element of the present invention. Referring to Figure 1, different programming schemes can be distinguished. On the left side of the curve, the resistance of the device remains substantially constant (i.e., high resistance state) until the device is reset by applying a reset pulse of sufficient energy to be applied. The device is then reset to its low resistance at its high resistance.
Since the amplitude of the applied current pulse is further increased, the resistance of the device increases from the low resistance state to the high resistance state. This increase can be gradual and vice versa, as indicated by the arrows located in either direction at the upper right or lower of the curve. In this arrangement, the ovonic memory element can be programmed to any resistor within the dynamic range of the resistance value by applying a current pulse of appropriate amplitude. This type of programming scheme is provided for analog, multi-state, directly recordable data storage, and this framework is also the programming scheme described in the Oshinsky patent.
The programming method of the present invention uses the left side of the curve in Fig. In such a scheme, the amplitude and duration of the current pulse used to program the device is important. The transition on the left side of the curve may be reversed as indicated by a single arrow on the left side of the curve. That is, when the device transitions from a high resistance state to a low resistance state, the device can not be reset to a high resistance state by applying a programming pulse of reduced current. Instead, the device may be reset to a high resistance state by a high-amplitude current pulse (i.e., a " reset pulse ") that drives the resistor on the upper right of the curve. As discussed above, the digital multilevel capability of the device when programmed in such a scheme results from the ability of the ovonic memory device to " accumulate " or " aggregate " the energy of the individual program current pulses applied to the device do.
The general purpose memory element of the present invention can store multiple bits of information in a single memory element and can also be used to provide different interconnect capabilities between " neurons " or nodes of an artificial intelligence network, as described below.
Turning now to Fig. 1 for additional detail, it is assumed that the device is in its high resistance state at the far left side of the characteristic curve of Fig. As described above, when a single reset pulse of sufficient energy is applied to the device, the reset pulse is reset in its low-resistance state. As noted above, what is noticed with the present invention and also with regard to the above-mentioned ovonic universal memory element is that the set current pulse, which sets the memory element in its high resistance state to its low resistance state, And that the application of the individual programming pulse does not actually change until the resistance of the memory device is greater than or equal to the " set period " described above for the entire duration of the programming pulse . When the last programming pulse carries the last increment of energy, the device is converted to a low resistance state.
Thus, the set pulse may be divided into a number of equal interval spacing pulses, each representing a data storage bit. For example, if it is desired to store a total of 8 bit bytes in a single memory element, the fractional interval pulse size and height may be divided to require eight pulses in one embodiment to switch the device to its low resistance state. As a result, eight storage levels can be pulsed from 0 to 7 to store a decimal value from "0" to "7". For example, if a 0 pulse is first applied to the element to store a " 0 ", 8 pulses are required to switch the element to its low resistance state, and the 8 pulses also indicate the number of pulses required to switch Can be read as " 0 " by subtracting from the number 8. Thus, the stored pulse may be determined in each case by subtracting the number of pulses required to convert the memory element to its low resistance state from the number 8. For example, if " 7 " is stored, then the number of pulses required to switch the element to its low resistance state is one and the stored decimal value is also " 7 ". Several logical protocols may be selected for storage and retrieval of information in the general purpose memory elements of the present invention.
For the sake of further explanation, the flow charts of Figs. 2, 3 and 4 are now performed as reference. 2 is a flowchart illustrating a method for storing multi-bit information according to an embodiment of the present invention. In this method, the memory write start operation starts in step S10. In step S11, the memory element may first be set to its high resistance state. This ensures that the memory element is fully set to its high resistance state before initiating a write operation. The multi-bit value or number to be stored is selected in step S12 and the pulse counter is set to a predetermined reference value corresponding to the number of pulses applied to the memory element. For the above example, the number of pulses may represent multi-bit binary numbers from " 000 " to " 111 " to provide storage of decimal values from " 0 " In step S13, the partial interval pulse is applied to the memory element. In step S14, the pulse count is added to the pulse counter and the number of pulses accumulated by the pulse counter is read.
In step S16, it is determined whether the number of pulses accumulated in the counter at that point is equal to the reference number of pulses stored in the counter. If the number of pulses read out from the pulse counter is equal to the reference number stored in the counter, the operation is stopped in step S16. If the number of pulses read out of the counter is less than the reference number stored in the counter, another partial interval pulse is applied to the memory element by returning to step S13, and the operation is also such that the number of partial interval pulses is equal to the stored reference number , And at that point the operation is stopped at step S16.
3 is a flow chart for a particular logical protocol consistent with that given in the above example for an eight pulse system to store binary numbers from " 000 " to " 111 " In this way, the memory read operation begins at step S20. In step S21, a partial interval pulse is applied to the memory element and thereafter the resistance of the memory element is then read in step S22. Then, in step S23, it is determined whether or not the resistance of the memory element is equal to or less than a threshold value corresponding to the low resistance state. If the memory element is not switched to a low resistance state, a pulse count is added to the pulse counter in step S24 and another partial interval pulse is applied to the memory element by returning to step S21.
Until the resistance of the memory element is determined to be less than or equal to a threshold indicating a transition to its low resistance state, the method moves to adding a pulse count to the pulse counter (S25) and also begins to reprogram the memory element do. The reprogramming of the memory element can be realized, for example, by applying the method shown in the flowchart of FIG. 2 described above.
Then, in step S26, the count from the pulse counter is read and the number of pulses read from the counter in step S27 is subtracted from the number of codes discussed in step S28. For example, if seven pulses are required to switch the memory element to its low resistance state, the number 7 is subtracted from the code number 8 to yield the stored binary value " 1 ". 5 pulses are required to switch the memory element to its low resistance state, the number 5 is subtracted from the number 8 to yield a decimal number 3 corresponding to the binary value " 011 ".
In the embodiment of Figure 3, the memory read operation is always initiated by the application of the fractional interval pulse. In this embodiment, the maximum number of pulses to be applied is equal to the maximum number value to be stored in the memory element. However, in another embodiment, the maximum number of pulses to be applied is one less than the maximum number value to be stored. In this embodiment, the resistance of the memory element may already be set to a low resistance level when a memory read operation is initiated.
The reading procedure for this embodiment is shown in the flowchart of Fig. In this embodiment, the memory read operation starts in step S31 and the resistance of the memory element is read in the first step S31 since the memory element can also be set to the low resistance state. If it is determined in step S32 that the resistance of the memory element is below a threshold indicating whether it is already in its low resistance state, then the stored binary value is read immediately in step S33. However, if it is determined in step S32 that the resistance of the memory element is above the threshold indicating that it is in its high resistance state, then the interspacing pulse is applied to the memory element in step S34, Is read in step S35. If the resistance of the memory element is still above the threshold determined in step S36, the pulse count is added to the pulse counter in step S37 and another partial interval pulse is applied to the memory element in step S34.
When the resistance of the memory element is switched to the low resistance state determined in step S38, a pulse count is added to the counter and the memory element is reprogrammed in step S38. The pulse counter is then read in step S39 and such read number is subtracted from the code number in step S40 to yield the stored binary number in step S33. The number of codes selected for this embodiment as given in the given 8-bit byte storage example is seven. Therefore, the zero pulse subtracted from the code number 7 is calculated as a decimal number 7 corresponding to the stored binary value " 111 ", and the seven pulses subtracted from the code number 7 are calculated as a decimal number 0 corresponding to the stored binary value " 000 & .
In each case, the logical protocol for recording the value to be stored according to the method of FIG. 2 is selected to correspond to the reading protocol of any of the embodiments of FIG. 3 or 4 selected or generally read and also authorized as discussed And may be selected to correspond to any other protocol that may be selected to store information based on the number of fractional spacing pulses.
Figure 5 shows an apparatus for carrying out the memory recording and reading method of the present invention. In the embodiment of FIG. 5, the memory read and write operations are performed by an apparatus comprising an addressing logic device 100 controlled by memory input / output and read and write instructions applied at input 102. Which is connected to a memory read and write addressing system 106 and to a pulse generator and counting device 104 which in turn are connected to a memory matrix 108 comprising a general purpose memory element of the present invention. The state of each memory element is addressed and determined and fed back to the pulse generator and counting device 104 by a memory state addressing and feedback system 110.
The memory read and write commands introduced at input 102 are performed using the method described above. For example, a read command at the input 102 of the memory input / output and addressing device 100 to read a multi-bit value selected from a selected memory location may be used to determine when the reference count has reached a pulse generator And a counting device 104 that generates a reference count and is responsive to feedback from the system 110. [ The memory read and write and address system addresses specific memory locations to which the read command is applied.
The memory state addressing and feedback and output device 100 determines the state of the memory element at an addressed memory location and also feeds back a signal for application of an additional fractional interval pulse from the device 104, 112 to read out the result stored in the memory. The write operation operates in the same way to perform the above-described method.
As described above, the multi-bit information stored in the general purpose memory element of the present invention according to the method discussed herein is stored in a form that is neither detectable nor inaccessible, resulting in the use of an apparatus as shown in the embodiment of Figure 5 The multi-bit information can not be retrieved except by using the method of the present invention. This in effect enables the storage data to be what the cipher is in the general purpose memory element.
In order to retrieve the stored data, the size and duration of the single fractional interval pulse must be known. Any attempt to determine this by experiment may result in no response at all if the pulse size is below the threshold or a complete guarantee of the stored data if the pulse is too large in size. Even though the pulse size and duration are known, the number of codes and protocols selected for storage of data should be known to enable appropriate reading from stored data. For example, if the protocol of the stored data requires a read as shown in the embodiment of FIG. 3 and the read is attempted using the protocol as shown in the embodiment of FIG. 4, erroneous readings may occur. Similarly, if the number of codes is 6 instead of 8, for example, erroneous readings may also occur. This additional safety criterion is in addition to that provided by a single fractional pulse characteristic that must first be satisfied in order to avoid complete destruction of the data without any recovery or recovery.
Several other protocols can also be imposed to provide a much more stable standard. For example, the apparatus of FIG. 5 may be configured such that an accurate reprogramming of each memory element may be required before reading from stored information at the output device 112 is enabled to precisely replace an individual stored multi-bit value. . In this embodiment, if the data is erroneously read from the memory matrix 108, the output device 112 can not deliver the stored information and the original data may be destroyed.
Thus, the embodiments discussed further utilize fractional spacing pulses of the same magnitude and duration. In another embodiment of the present invention, the pulses differ from one another in a number of ways. In general, a more complete discussion of parameters that affect a single characteristic of a fractional interval pulse and a programming energy pulse will now be presented.
The general purpose memory element of the present invention comprises a volume of phase change memory material with a low resistance state detectably distinguishable from a minimum high resistance state. The high resistance state is characterized by a high electrical resistance and the low resistance state is characterized by a low electrical resistance that is detectably distinguishable from a high electrical resistance state.
At least one volume fraction of the volume of the memory element may be converted from a high resistance state to a low resistance state in response to a single energy pulse input referred to as a " set energy pulse ". The set energy pulse has sufficient amplitude and duration to convert a volume fraction of the memory material from a high resistance state to a low resistance state. The amplitude of the set energy pulse is defined as a " set amplitude " and the duration of the set energy pulse is defined as a " set period ". The act of converting the volume of the memory material from the high resistance state to the low resistance state is referred to as " setting (or " setting, etc.) the volume of the memory material from the high resistance state to the low resistance state.
Generally, as discussed herein, the " energy " applied to the volume of memory material is not limited to electrical energy, but may be any form, including particle beam energy, optical energy, thermal energy, electromagnetic energy, acoustic energy, . Preferably, the electrical energy takes the form of a current or voltage, and the set energy pulse has an amplitude equal to the " set amplitude " necessary and sufficient to set the volume of the memory material from the high-resistance state to the low- Lt; / RTI > is a set current pulse having the same period as "
Without wishing to be bound by theory, it is believed that the energy applied to the memory material by the set energy pulse changes the local order of at least a portion of the volume of the memory material. In particular, the applied energy causes at least a portion of the volume of the memory material to change from a less ordered " amorphous " state to a more well-ordered " crystalline " state. As used herein, the term " amorphous " refers to a condition that is less structurally or more orderly than monocrystalline and also has detectable properties such as higher electrical resistivity. As used herein, the term " crystal " refers to a condition that is more structurally more ordered than amorphous and also has at least one detectably different property, such as a lower electrical resistivity. Preferably, the low electrical resistivity crystalline state is detectably distinguishable from the highly resistive amorphous state. The single set energy pulse is an energy pulse having amplitude and duration sufficient to crystallize the memory material to the required extent such that the energy pulse is converted from its high resistance state to its low resistance state. The actual amplitude and duration selected for the set amplitude and the set period is not limited to, but is not limited to, the volume size of the memory material, the memory material used, the type of energy used, and the means for applying the energy to the memory material It relies on any factor of.
As described above, the ovonic memory element can be set to a low resistance state from a high resistance state by a single energy pulse referred to as a " set energy pulse ". The memory element of the present invention may also be set to a low resistance state from a high resistance state by a plurality of energy pulses, referred to as " program energy pulses " (to distinguish them from the set energy pulses). Unlike the set energy pulse, each of the plurality of program energy pulses is insufficient to set the memory material from the high resistance state to the low resistance state. However, each of the program energy pulses is sufficient to change at least a portion of the material sufficiently to convert from a high-resistance state to a low-resistance state due to the accumulation of a plurality of program energy pulses.
Again, not wishing to be bound by theory, each of the plurality of program energy pulses applied to the volume of memory material causes the material to " change " by causing a certain amount of crystallization (i. E., Nucleation and / or crystal growth) "I think. The amount of crystallization caused by each of the program energy pulses alone is insufficient to change the memory element from its high resistance to its low resistance state. However, the " accumulated " crystallization caused by the plurality of program energy pulses is sufficient to set the memory element together in its high resistance state to its low resistance state. Essentially, the volume portion of the memory material " accumulates " changes (i.e., crystallization) caused by each of the individual program energy pulses applied to the device.
In general, the amplitude and duration of a plurality of partial intervals or program energy pulses may each be different. In one embodiment, the amplitudes are all equal and also preferably set equal to the amplitude of the set energy pulse (i.e., the "set amplitude"). Each period of the program energy pulse is selected by dividing the time interval, or " set period, " of the set energy pulse into a plurality of partial intervals. (Thus, the total period of all the sub-intervals is the same as the " set period "). The duration of each program energy pulse is set equal to one of the sub-intervals.
Thus, a plurality of partial intervals or program energy pulses may be used to set the memory element from a high resistance state to a low resistance state, where each of the program energy pulses has an amplitude equal to the amplitude of the set energy pulse Each of the program energy pulses has the same period as one of the partial intervals. As described above, the resistance of the memory element does not actually change from the high-resistance state until the last one of the program energy pulses is applied to the volume of the memory material. When the final program energy pulse is applied, the device is converted to a low resistance state.
Note again that the energy applied to the volume of memory material can be in the form of a pulse of current. Thus, the memory element can be set to a low resistance state from a high resistance state by a plurality of " program current pulses ", wherein the individual program current pulses are insufficient to set the device alone. In one embodiment, the time defined by the duration of the " set current pulse " may be divided into sub-intervals. A plurality of program current pulses may be applied to the memory material wherein each program current pulse has an amplitude equal to the amplitude of the set current pulse and each program current pulse has a duration equal to one of the partial intervals. The device can be set after the last program current pulse is applied.
In one embodiment, the data may be written to the memory element by applying one or more program energy pulses to the volume of the memory material. Generally, the amplitude and duration of the program energy pulse used may all be different. The amplitude of each program energy pulse may be selected equal to the " set amplitude " of the set energy pulse described above. The duration of each program energy pulse is insufficient for each pulse to set the volume of memory material from the high resistance state to the low resistance state and the total duration of all of the program energy pulses is less than or equal to the set duration of the set energy pulse .
As discussed, the energy can be applied to the volume of the memory material in the form of a current pulse. Referring back to Figure 1, the device switches from a high resistance state to a low resistance state because the amplitude of the applied current pulse increases with sufficient amplitude. A single current pulse sufficient to set the memory material from a high resistance to a low resistance state is referred to as a " set current pulse " having an amplitude referred to as the " set amplitude "
Data can be written to the memory element by applying one or more " program current pulses " to the volume of memory material, where each program current pulse is insufficient to set the device. Generally, the amplitude and duration of the program current pulse may all be different. In one embodiment, the amplitude of each program current pulse is selected equal to the set amplitude defined above. The duration of each program current pulse is also such that (1) each pulse alone is insufficient to convert the material from its high resistance to its low resistance, and (2) the entire duration of all of the program current pulses is & &Quot; or " equal "
In one implementation of the current programming method, as described above, the time defined as the " set period " is divided into partial intervals. The number of partial intervals is chosen to be one less than the desired number of total possible programming states. For example, if five total programming states are required, the time interval " set period " is divided into four subintervals (so that the total duration of all four subintervals is equal to the " set period "). Preferably, the partial intervals are all the same. (However, other executions are possible using unequal subintervals).
The element can be programmed to a desired " programmed state " by applying one or more program current pulses, wherein each program current pulse has the same duration as one of the partial intervals, and the amplitude is " Amplitude ". In the example using five states in total, the memory element is in state I if no program current pulse is applied and the memory element is in state II when one program current pulse is applied, and when two program current pulses are applied The memory element is in state III and the memory element is in state IV when three fractional spacing pulses are applied and the memory element is in state V when four fractional spacing pulses are applied.
Note that the resistance of the memory material does not actually change until the total period of the partial interval pulse is equal to or greater than the " set period ". In this example, the resistance does not actually change until four partial interval pulses are applied. When four pulses are applied, the resistance of the memory element can be converted from a high resistance state to a low resistance state.
The programmed state of the memory element may be read by applying additional program current pulses and counting the number of additional pulses applied until the memory material is set to its low resistance state. In this example, if one program current pulse is first applied to write data to the memory element, the programmed state is state II. In this case, three additional program energy pulses must be applied to set the memory element in a low resistance state. The programmed state can be determined by subtracting the number of additional pulses needed (in this case 3) from the total number of possible states (in this case 5). Thus, the programmed state is 5-3 = 2 (ie, state II).
Therefore, as discussed in connection with the above-described embodiments, the device can be read by first determining if a volume fraction of the memory material is in a low resistance state. If it is not in the low resistance state, an additional program energy pulse is applied and the resistance of the device is again determined. If the memory element is not still in a low resistance state, another additional program energy pulse is applied and the resistance of the device is again determined. This procedure is repeated until it is determined that the device is in a low resistance state. The number of additional program current pulses required to set the device is counted (i.e., the counter can be incremented while each additional program energy pulse is required), and this number is also used for the determined programmed state.
The method of programming further comprises erasing data from the memory element by applying a " reset energy pulse " to the volume of the memory material. The reset energy pulse is an energy pulse sufficient to change the resistance of the volume of the memory material from the low resistance state to the high resistance state. This is preferably an energy pulse sufficient to change at least a portion of the volume of the memory material from a more well ordered crystalline state to a less ordered amorphous state. Note that the program energy pulse (or program current pulse) described above is sufficient to change the resistance of the memory material from a low resistance state to a high resistance state. As described above, the form of energy can be current. Thus, the " reset current pulse " is a current pulse sufficient to change the resistance of the volume of the memory element from a low resistance state to a high resistance state.
It should be noted that while most of the above discussion is termed current pulses, any form of energy may be used to perform the programming method of the present invention. The forms of energy include electrical energy, optical energy, electron beam energy, thermal energy, electromagnetic energy, acoustic energy, and pressure energy. As noted above, in one embodiment of the present invention, the method of programming discussed employs a pulse of current to program the memory element that applies the current pulse, and the memory element of the present invention is programmed to program the volume of the memory material And means for transferring electrical energy to at least a portion of the volume of the at least one volume. In general, " current " is defined as the flow of charge. Examples of charges are electrons, protons, positives and anions, and any other form of charged particles. The flow of charge may be due to a beam of charged particles, such as an electron beam or a quantum beam.
In one embodiment of the present invention, the transmission means is a first contact portion and a second contact portion. The individual contacts are adjacent to the volume of the memory material. As used herein, a contact is " adjacent " to the volume of the memory material when at least a portion of the contact is actually touching the memory material.
In another embodiment of the present invention, the first and second contacts are a pair of spaced apart planar contacts adjacent to the volume of memory material. Each contact can be made up of one or more thin film contact layers. 6 shows a cross-sectional view of an embodiment of the memory element formed on a monocrystalline silicon semiconductor wafer 10. The memory element includes a memory material (36), a first spaced apart contact (6) adjacent the volume of memory material, and a second spaced apart contact (8A) adjacent the volume of memory material . In the illustrated embodiment, the first and second contact portions 6, 8A are planar contact portions. At least one of the contacts 6, 8A may comprise one or more thin film layers. An example of a memory element in which the first and second contacts 6, 8A comprise two thin film layers is disclosed in commonly assigned U.S. Patent Application Serial No. 08 / 739,080, the disclosure of which is incorporated by reference.
The memory material layer 36 is preferably located at a thickness of about 200 A ⁰ to about 5,000 A ⁰ , more preferably about 250 A ⁰ to about 2,500 A ⁰ , and most preferably about 250 A ⁰ to about 500 A ⁰ Thick.
The memory element shown in Fig. 6 can be formed as a multi-step process. The contact layer 8A and the insulating layer 46 are first deposited and etched so that the insulating layer 46 is in the contact area between the memory material 36 and the contact layer 8A. The memory layer 36 and the contact layer 6 are then deposited and the entire stacks 8A, 46, 36 and 6 are etched to a selected size. It is the insulating material layer 39 that is deposited on top of the entire structure. Examples of insulating materials are SiO _2, Si ₃ N ₄ and tellurium oxide sulfide (for example, TeOS). An insulation layer 39 is etched and an aluminum layer 42 extends perpendicular to the conductors 12 and also forms a second electrode grid structure 42 that completes the XY grid connection to each memory element. do. It is covered over the complete integrated structure is a plastic material, such as the upper capsule layer or a polyamide consisting of suitable capsule material such as Si ₃ N _4, which seals the structure, and the other outer element against the humidity that may cause a drop in performance . The Si ₃ N ₄ encapsulant material may be deposited using, for example, a low temperature plasma deposition process. The polyamide material can be spin coated and can also be baked after deposition by known methods for forming a layer of capsule material.
In yet another embodiment of the present invention, the transmission means comprises at least one " tapered " The tapered contact is a tapered contact with respect to a peak adjacent to the volume of the memory material. An embodiment of a memory element utilizing a tapered contact is disclosed in commonly assigned U.S. Patent No. 5,697,112 to Obersynski et al., The disclosure of which is incorporated by reference.
The transmission means may also be at least one field emitter. Field emitters are described by Gibson et al. In U.S. Patent No. 5,557,596, the disclosures of which are incorporated by reference. The field emitter is tapered with respect to the peak located close to the volume of the memory material. As defined herein, the term " in close proximity " means that the field emitter is not actually in contact with the volume of the memory material. The field emitter is preferably located between about 50 A ⁰ and about 100,000 A ⁰ from the volume of the memory material. It is more preferably positioned between about ⁰ and about 50,000A ⁰ 500A from the volume of the field emitter wherein the memory material. The field emitter generates an electron beam from its tapered peak. As discussed in the '596 patent, the electron beam can be emitted from the field emitter in several different ways. A circular gate may be placed around the field emitter and a voltage may be placed between the field emitter and the gate. Alternatively, the voltage may be between the field emitter and the actual volume of the memory material. In another embodiment, a contact (such as a planar contact) may be positioned adjacent to the volume of the memory material and also be spaced apart from the field emitter. A voltage may be placed between the field emitter and the planar contact so that the electron beam is applied to the volume of the memory material and impinges on the memory material. More than one field emitter may be used.
The field emitters can be manufactured in various ways. One method is discussed in " Physical Properties of Thin-Film Field Emission Cathodes with Molybdenum Cones " by Spint et al., Published in Applied Physics, Vol. Other methods are discussed in "Fabrication and Characteristics of Si Field Emitter Arrays," by Betsui, published in Digest 4 of the Vacuum Microelectronics Association, 1991, page 26, Naka-hama, Japan.
A partial vacuum may exist between the volume of the field emitter and the memory material. As discussed in the '596 patent, the partial vacuum is at least 10 ^-5 torr. Methods for fabricating field emitters in vacuum cavities are known in the art. Techniques are discussed in " Silicon Field Emission Transistors and Diodes " by Jones, published in the IEEE Newsletter, 1992. 1051, 15, Ingredients, Hybrid and Manufacturing Technologies. Alternatively, the gas can be placed between the field emitter and the volume of the memory material.
In yet another embodiment of the present invention, the means for transferring the current is a tunneling contact that is positioned adjacent to the volume of the memory material. Tunneling contacts can be similar to field emitters. And may be tapered relative to a positioned peak that is close to the volume of the memory material. The tunneling contact is not actually in contact with the memory material, but the contact is located within the quantum mechanical tunneling distance. Preferably this distance is less than 50A ⁰ .
Examples of phase-change materials are proposed in U.S. Patent Nos. 3,271,591 and 3,530,441, the disclosures of which are incorporated by reference. Other examples of phase-changing materials are disclosed in commonly assigned U.S. Patent Nos. 5,166,758, 5,296,716, 5,534,711, 5,536,947, 5,596,522, and 5,687,112 , The disclosure of which is hereby incorporated by reference.
The phase-change material is preferably " non-volatile ". As used herein, " nonvolatile " means that the phase-change material can sustain the integrity of the information stored by the memory cell (within the limits of the selected error) without the need for periodic recovery.
The volume of the memory material may comprise a mixture of a dielectric material and the phase-change material described above. A " mixture " may be a heterogeneous mixture or a homogeneous mixture. The mixture is preferably a homogeneous mixture. A memory material comprising a mixture of a phase-change material and a dielectric material is disclosed in commonly assigned U.S. Patent Application No. 09 / 063,174, the disclosure of which is hereby incorporated by reference.
By " phase change material " discussed herein, it is believed that by applying energy in an electrical or other fashion, between the more localized orders (more crystalline states) and other detectable states with smaller local orders (more unstructured or more amorphous states) Is defined as a material that can be reversed. The phase change material of the present invention also exhibits a characteristic capable of accommodating energy inputs below the level required to cause a detectable change in the local order, but nevertheless a change in detectable change in the local order after a plurality of energy inputs is applied And also causes a change in the structure of the resulting material.
Preferably, the phase-change material of the present invention comprises at least one element selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof. do. The phase change material preferably comprises at least one chalcogen element and may also comprise at least one transition metal element. Preferably, the chalcogen element is selected from the group consisting of Te, Se and mixtures or alloys thereof. More preferably, the chalcogen element is a mixture of Te and Se.
The term " transition metal " as used herein includes elements 21 to 30, 39 to 48, 57 and 72 to 80. Preferably, the transition metal element is selected from the group consisting of Cr, Fe, Ni, Nb, Pd and Pt and also a mixture or alloy thereof. Most preferably, the transition metal is Ni. Specific examples of such multi-element systems are described below for Te: Ge: Sb systems with and without Ni and / or Se.
The size of crystals existing in the semiconductor bulk and memory material is relatively small, preferably less than about 2000A ^0, more preferably is between about 50A ⁰ and 500A ^0, also most preferably from about 200A ⁰ To 400 A < ^{0 &} gt ;.
Many of the phase-change materials of the present invention tend to form larger and smaller crystals per unit volume. The crystallite size of the widest area of the first exemplary material embodying the present invention becomes much smaller than about 2000A ^0, was generally found to become smaller than the characteristic of 5,000A to 2000A ^{0 0} Area of the conventional material. The crystal size is defined herein as the diameter of the crystal or the diameter of the " characteristic dimension " corresponding to the diameter of which the crystal is not spherical.
It has been determined that the high-resistance state composition of the TeGeSb material satisfying the criteria of the present invention is generally characterized by the actual reduced concentration of Te in relation to that proposed in the prior art electrically erasable memory material. Examples of TeGeSb materials are disclosed in commonly assigned U.S. Patent Nos. 5,534,711, 5,536,947 and 5,596,522. In one composition that actually provides improved electrical switching performance characteristics, the average concentration of Te in the deposited material is less than 70%, typically less than about 60%, and also ranges from about 23% to about 58% Te And most preferably from about 48% to about 50% Te. The concentration of Ge is about 5% or more, and ranges from about 8% to about 30% of the material, and is generally less than 50%. More preferably, the concentration of Ge ranges from about 8% to about 40%. In this composition, the remnant of the major constituent element is Sb. The percentage given is the atomic percentage which is a total of 100% of the atoms of the constituent element. Thus, these compounds can be characterized as Te _a Ge _b Sb _{100- (a + b)} . This ternary Te-Ge-Sb alloy is a useful starting material for the improvement of additional phase change materials with much better electrical properties.
The phase-change material of the present invention preferably comprises at least one chalcogen and may also comprise one or more transition metals. The phase change material comprising a transition metal is essentially a modified form of phase change material in the Te-Ge-Sb ternary system. That is, basically the modified phase-change material consists of a modified form of the Te-Ge-Sb phase-change alloy. This basic modification is achieved by bonding the transition metal to the basic Te-Ge-Sb ternary system with or without additional chalcogen elements such as Se. Generally, basically modified phase-change materials are included in two categories.
The first category is a phase change material comprising Te, Ge, Sb and a transition metal as _a (Te _a Ge _b Sb _{100- (a + b)} ) _c TM _100-c ratio, where the subscripts are 100 %, Wherein TM is at least one transition metal, a and b are as described above for the basic Te-Ge-Sb ternary system, and c is between about 90% and about 99.99%. The transition metal preferably comprises Cr, Fe, Ni, Nb, Pd, Pt and mixtures and alloys thereof.
The second category is a phase change material comprising Te, Ge, Sb, Se and transition metal as a ratio (Te _a Ge _b Sb _{100- (a + b)} ) _c TM _d Se _100- The subscripts are in atomic percentages that are 100% of the total elements, TM is at least one transition metal, a and b are as described above for the basic Te-Ge-Sb ternary system, and c is about 90% To about 99.5%, and d is between about 0.01% and 10%. The transition metal may preferably comprise Cr, Fe, Ni, Pd, Pt, Nb and mixtures and alloys thereof.
The phase-change material actually has a non-volatile set resistance value. However, if the resistance value of the phase change material drifts from its original set value, a " compositional modification " described below can be used to compensate for this drift. As used herein, the term " nonvolatile " refers to a state in which the set resistance value remains substantially constant during a write period. Of course, software (including the feedback system described below) can be used to ensure that " drift " never occurs outside the limits of the selected error.
Is defined herein to include any means of constructively deforming the phase-change material to produce a practically stable resistance value, including the addition of a bandgap magnifying element to increase the resistivity of the material. One example of a synthetic deformation is to include a synthetic heterogeneity categorized in terms of thickness. For example, the volume of the phase change material can be classified as a second Te-Ge-Sb alloy consisting of the first Te-Ge-Sb alloy and another composition. A synthetic classification may take any form that reduces set resistance drift. For example, the synthetic classification need not be limited to the first and second alloys of the same alloy system. The classification may also be achieved by two or more alloys. The classification may be constant, continuous or non-continuous or non-continuous. A specific example of a synthetic classification resulting in reduced resistance drift includes a constant and continuous classification of Ge ₁₄ Sb ₂₉ Te _{57 on} one side and Ge ₂₂ Sb ₂₂ Te _{56 on the} other.
Another way to use synthetic deformation to reduce resistance drift is to layer the volume of the phase-change material. That is, the volume of the phase change material is a number of discontinuous, and may be in the form of a relatively thin layer of different components. For example, the volume of the phase-change material may comprise more than one layer, and each pair of layers is formed of another Te-Ge-Sb alloy. Again, any combination that results in a substantially reduced resistance drift, as in the case of a sorted compound, can be used. The layer can be of similar thickness or of different thickness. Any number of layers may be used and multiple layers of the same alloy may be provided within the volume of the memory material, whether contiguous or spaced apart from each other. Also, any number of layers of different alloy components may be used. A specific example of synthetic layering is the volume of memory material comprising the other layer pair Ge ₁₄ Sb ₂₉ Te ₅₇ and Ge ₂₂ Sb ₂₂ Te ₅₆ .
Another form of synthetic non-homogeneity for reducing resistive drift is achieved by combining synthetic classification with synthetic layering. More specifically, the synthetic classification already mentioned can be combined with any of the above described synthetic layering to form a stable volume of memory material. Exemplary volumes of the phase-shifting material utilizing this combination are (1) the volume of phase change material comprising the discontinuous layer Ge ₂₂ Sb ₂₂ Te ₅₆ after the sorted composite Ge ₁₄ Sb ₂₉ Te ₅₇ and Ge ₂₂ Sb ₂₂ Te ₅₆ , And (2) the volume of the phase change material including the discontinuous layer Ge ₁₄ Sb ₂₉ Te ₅₇ and the classified compounds Ge ₁₄ Sb ₂₉ Te ₅₇ and Ge ₂₂ Sb ₂₂ Te ₅₆ .
The memory material may be fabricated by methods such as sputtering, vapor, or chemical vapor deposition (CVD), which may be enhanced by plasma techniques such as RF glow discharge. The memory material may be most preferably prepared by RF sputtering or vapor. This can be done by a multiple source sputtering technique that uses a target of multiple targets, usually a phase change material, and a target of dielectric material. By these targets disposed opposite the substrate, sputtering is performed while the substrate is rotated relative to each target. A target including a phase change material and a dielectric material can be further utilized. Furthermore, the row of substrates can be used to control the morphology of the phase change material in the formed memory material by affecting crystal growth as well as crystal aggregation by surface mobility.
Another important application of the general purpose memory element of the present invention is a parallel processing network which can be used in, for example, neural networks and artificial intelligence computing systems. The parallel processing network includes vertically interconnected parallel distributed processing arrays that include a plurality of stacked unit cell metrics. Each unit cell is in data transfer transmission state with at least one other unit cell in the adjacent plane. Preferably, the unit cells in a given plane may also be interconnected to some extent. In this way, a high degree of relevance can be achieved between individual unit cells of the array. Parallel processing networks are discussed in commonly assigned U.S. Patent No. 5,569,661, the contents of which are incorporated herein by reference.
Neural network calculations are based on simulating computational methods used by animal nerves. The neural network receives electrical signals from a number of different nerves. This assigns weight or importance to each of these signals. Assigned weights are "learned" by the system through experience. If the sum of the weighted inputs exceeds the threshold, the nerve is fired. This ignition transmits electrical signals to the input of a number of other neurons.
The general purpose memory elements of the present invention can be coupled to a neural network system to operate in much the same way. In such an embodiment, a plurality of weighted pulses are applied to the universal memory element until a threshold is reached and the switch is switched or " ignited. &Quot; An advantage of the present invention is that the pulses can not be simultaneously applied. The result of each pulse is stored in nonvolatile form and remains stored until the next pulse is applied to add to the already stored pulse. Thus, the neural network operation can be achieved using continuous pulses applied in any time pattern.
It provides a simple and regular structure as a memory array type to perform neural logic functions. One embodiment of the present invention that is coupled to a neural network processor is shown in FIG. In this embodiment, the arrangement of the general purpose memory elements 200 of the present invention is formed by an isolation diode 202. The feedback paths 204 and 206 consist of a row input of the array at the column output of the array via the sense amplifier 208 and the current driver 210 shown.
When the individual memory element 200 is in its high resistance state, the degree of connection between the row and column to which it is connected is low due to the high resistance.
The weighted pulse is applied as a current driver to the universal memory element 200 via isolation diode 202 using a control strategy that determines how the pulse is applied and how the weight is assigned to it. The results of these pulses are stored incrementally in each memory element. When the selected threshold level reaches any given memory element, it switches to or "ignites" its low resistance state to increase the level of connectivity between row and row connected by the installed low resistance path.
A unit cell that can be used in an embodiment other than the present embodiment is shown in Fig. Turning now to FIG. 8, there is shown a typical unit cell that may be used in the present invention. The unit cell includes a data input line (10) and a data output line (12). The transmission between the two lines 10 and 12 is made by the general purpose memory element 14 of the present invention. FIG. 9 shows, in schematic form, a portion of a stacked arrangement of two metrics 140 and 142, each including unit cells vertically interconnected by 44. FIG. Similar lamination matrices are contemplated within the scope of the present invention for other unit cells shown herein.
The unit cell further includes an isolation device such as a diode (16). Typically, the unit cells are arranged in an array such that the data input 10 and the data output line 12 comprise a series of rows and columns, and in this embodiment also the isolation device 16 is between adjacent unit cells It functions to prevent crosstalk. The isolation device is represented as diode 16 and includes a thin film diode, such as a polysilicon diode, although amorphous, polycrystalline or crystalline diodes made of various other materials, which may themselves be other devices such as transistors, can do. When a structure comprising a chalcogenide and a polycrystalline diode is fabricated, the diode is typically deposited as an amorphous device using thin film technology and they are crystallized continuously. In accordance with the present invention, it has been found advantageous to crystallize the diode material using short pulses of light from a laser or similar light source to rapidly crystallize the material without damaging the chalcogenide material.
The cells of FIG. 8 are part of a matrix of generally the same cells arranged in rows and columns. The processor of the present invention comprises a stacked array of the matrices and also at least some of the cells in the first matrix are interconnected with cells in the second matrix such that the data output of the cells on the first side 140 is on the second side 142 ) Communicates with the input of the cell.
FIG. 9 shows, in schematic form, a portion of a stacked arrangement of two metrics 140 and 142, each including unit cells vertically interconnected by 44. FIG. Similar lamination matrices are contemplated within the scope of the present invention for other unit cells shown herein.
The unit cell further includes an isolation device such as a diode (16). Typically, the unit cells are arranged in an array such that the data input 10 and the data output line 12 comprise a series of rows and columns, and in this embodiment also the isolation device 16 is between adjacent unit cells It functions to prevent crosstalk. The isolation device is represented as diode 16 and includes a thin film diode, such as a polysilicon diode, although amorphous, polycrystalline or crystalline diodes made of various other materials, which may themselves be other devices such as transistors, can do. When a structure comprising a chalcogenide and a polycrystalline diode is fabricated, the diode is typically deposited as an amorphous device using thin film technology and they are crystallized continuously. In accordance with the present invention, it has been found advantageous to crystallize the diode material using short pulses of light from a laser or similar light source to rapidly crystallize the material without damaging the chalcogenide material.
The cells of FIG. 8 are part of a matrix of generally the same cells arranged in rows and columns. The processor of the present invention comprises a stacked array of the matrices and also at least some of the cells in the first matrix are interconnected with cells in the second matrix such that the data output of the cells on the first side 140 is on the second side 142 ) Communicates with the input of the cell.
Note that the vertical according to 44 of Figure 9 provides a means for communication between the data input line 10 of the first unit cell and the data output line 12 of the second unit cell in the matrix 142 in the matrix 140 do. As shown in FIG. 9, communication occurs through the volume of the memory material of at least one cell of the unit cell. The connection between the data input line 10 and the matrix 142 and the data output line 12 at the matrix 140 is determined by the distinguishably programmed state of the chalcogenide based on the multivalued- do.
The data processing network further includes means for programming each unit cell for the programmed state. The means for programming may include means for applying an electrical signal to the volume of memory material in each unit cell. 10 shows a unit cell including a stimulus 18 input and a suppression 20 input and a data output line 12. [ This embodiment further comprises a universal memory multivalue-digital storage element 14 and an isolation device 16 connected to each of the input lines 18,20. This type of unit cell can receive anode data that stimulates or suppresses the output response. In the previous unit cell, the ovonic memory multivalue-digital storage element is programmed by a signal applied to data input lines (10, 18, 20) and data output lines (12).
11 shows another embodiment of the present invention which further includes a field effect transistor 22 with source and drain in series with the data input line 10 and an ovonic memory multi-value storage element 14. The gate 24 of the transistor is energized by a separate control line 26. In this type of unit cell, the data imposed on the control line 26 further transforms the data on the input line 10 to further affect setting and resetting the ovonic memory multi-value storage element 14 Or supplement.
Referring now to Figure 12, another embodiment of a unit cell is shown. This cell includes a stimulus 18 and a suppression line 20 each having a field effect transistor 22 having a source and a drain in series with a general memory multi-value-digital storage element 14 and an isolation diode 16 do. The gate 24 of each transistor 22 is controlled by a common control line 28. In this type of unit cell operation, the common control line 28 receives input data, such as data from a pixel of the image sensor, for example, and also transmits this data to the unit cells. The stimulus and suppression data on the individual lines 18,20 modifies the response of the cell to the data to produce an output in communication with other cells in the processing network.
Note that the parallel processing network of the present invention includes means for parallel input of a plurality of data. The means for parallel input of a plurality of data further comprises means for sensing an already selected species and for generating an electrical signal in response thereto.
The means for parallel input of multiple data may also include means for parallel input of electrical data. Furthermore, the means for parallel input of multiple data may comprise means for parallel input of optical data. Means for parallel input of optical data may comprise means for converting optical data into electrical data. The means for converting optical data into electrical data may comprise a light responsive body of a silicon alloy material.
It should be understood that the foregoing is an example of a specific neural network unit cell structure that can be used in the present invention. Other modifications of the unit cell may be similarly utilized. The present invention includes all parallel distributed processing arrays with interconnected unit cells comprising a general purpose memory multi-value-digital storage element of the present invention. The present invention easily provides itself to the manufacture of various other parallel processing devices as well as a neural network calculation system.
Within the context of the present invention, the volume of memory material is preferably a chalcogenide base material. It should be generally understood that the chalcogenide base material contains one or more chalcogenide elements here and that the chalcogenide element also includes elements from Group IVa of the Periodic Table. The volume of the memory material may include one or more elements from the group consisting of carbon, silicon, germanium, tin, lead, phosphorus, arsenic, antimony, florin, and bismuth.
Another use of the memory element of the present invention includes a data storage arrangement. An upper aspect of the structure for storing a plurality of memory element data is shown in FIG. As shown, the device forms an X-Y matrix of memory elements. Horizontal strip 12 represents the X set of X-Y electrode grids addressing each element. Vertical strip 42 represents the T set of addressing lines.
Each memory element is electrically isolated from other elements by using any other type of isolation element. 14 is a schematic diagram of a memory device layout diagram showing how electrical isolation is achieved using a diode. The circuit includes an X-Y grid with a memory element 14 that is electrically interconnected in series with an isolation diode 16. The address lines 12 and 42 are connected to an external addressing circuit in a manner well known to those skilled in the art. The purpose of the isolation element is to allow the discrete memory element to read and write without interfering with the information stored adjacent to or away from the memory element of the metric.
15 shows a memory matrix 51 of the present invention formed on a part of the single crystal semiconductor substrate 50 and here. What is formed on the same substrate 50 is the addressing matrix 52 which is suitably connected to the memory matrix 51 by the integrated circuit connection portion 53. The addressing matrix 52 includes signal generating means for defining and controlling settings and read pulses applied to the memory matrix 51. [ Of course, the addressing metric 52 may be concurrently formed with the solid state memory matrix 51 and may be combined.
In another embodiment as shown in FIG. 16, the general purpose metrics element of the present invention is incorporated as a connection capability element in a node network of a neural network system. 16, the general purpose memory element 302 of the present invention is configured as three terminal devices having a control terminal 304, a signal terminal 306, and a common control and signal terminal 308. [ Terminals 304 and 306 are connected to one electrode 310 of device 302 and terminal 308 is connected to another terminal 312 of the device. Electrodes 310 and 312 are connected across phase change element 314 to control switching thereof in a manner previously described.
Terminals 306 and 308 are connected to nodes 316 and 318 of the node network of the neural network system, respectively. Thus, the memory element 302 is coupled to control the connection capability between the nodes 316 and 318. That is, the connection capability between nodes 316 and 318 is minimized if element 302 is in its high-resistance state, and the connection between nodes 316 and 318 when element 302 is in its low- The ability is maximum.
Control of the element 302 is realized as an embodiment represented by a neural network control system 32 coupled to the electrode 312 via a control terminal 394 and to the electrode 312 via a common terminal 308. [ The weighted pulses are applied by the neural network control system 320 to the universal memory element 302 via terminals 304 and 308 using a control strategy that determines when pulses are applied and how weights are assigned to them . The results of these pulses are incrementally stored in the memory element 302. When the selected threshold level reaches the memory element 302, it switches to or " ignites " its low resistance state to increase the level of connectivity between nodes 316 and 318. If desired, the blocking diode may be interposed between the node 316 and the terminal 306 to isolate the node network from the control pulse applied to the control terminal 304.
Terminals 304, 306, and 308 may be located adjacent to element 302 or further away from the element to facilitate the connection of circuitry to other devices. For example, in an integrated circuit application of the embodiment of FIG. 16, the terminals 304, 306, and 308 may be used as elements and metallization steps that are most suitable for forming the integrated circuit when performing and providing internal and external connections to other devices and circuits Lt; / RTI >
The embodiment of FIG. 16 shows only a pair of nodes in a node network including a plurality of nodes, and all or any selected portion of the nodes in the node network are connected by the connection capability element of the present invention in the manner shown in FIG. It should be understood that they can be interconnected.
As already discussed, the method of programming of the present invention is applicable to the field of encryption. One of the basic methods of encryption is the use of encryption keys. This key is used to encrypt and decrypt the transferred information. By using the key, the problem is that when this key is known as a third party, the encrypted subject can be decoded into a third party. Currently the best encryption key is hundreds or thousands of digits. It is impossible for someone to remember such a long number. Thus, the encryption key for the data transmitted over the Internet can be recorded, for example, on the hard drive of the computer associated with the data transmission. Storage on the hard drive simply creates a number that can be accessed by the person accessing the computer by reading information directly from the hard drive. Therefore, the encryption key can be easily obtained.
The use of the inventive general purpose memory device programmed by the techniques disclosed herein to store the encryption key eliminates the problem of unauthorized reading of the encryption key. That is, because of the destructive readings required to determine the state of each memory element, the person attempting to read the key programmed into the inventive general purpose memory chip array may determine the program pulse width, amplitude, etc. used to program the memory element If not, he will not be able to easily read the data stored in the memory element.
For example, the assumption in programming the ovonic memory element was that 8 pulses of 40 nanoseconds were used as the total number of pulses required to switch the device from a high resistance state to a low resistance state. Also assuming that the memory is programmed with five pulses, three or more pulses are required to set the device for the entire time that still requires 120 nanoseconds. Now assume that a person who does not know how to program the device will attempt to read the program state of the device. The person will not know that the device has been programmed with a 40 nanosecond pulse. Thus, if the person tries to read the device, it will not be able to pick the appropriate programming pulse length. For example, suppose that person selects a 60 nanosecond programming pulse to try and read the device. The person will know that the device requires only twice as many pulses before the device switches from a high resistance state to a low resistance state. So even if the person does not know the total number of programming states, he gets 6 inaccurate results instead of 5 programs. Additionally, if the total number of programming states is not known, the number of pulses required to set the device to a low resistance state may not be known.
Thus, it is clear that the programming state of the device can not be read without knowing the programming parameters of the memory element.
It should be understood that the disclosure herein has been suggested in the context of a detailed embodiment discussed for the purpose of providing a full and complete disclosure of the invention and that the detailed description can not be construed as limiting the true scope of the invention as defined in the appended claims .

权利要求:
Claims (21)
[1" claim-type="Currently amended] Change memory element having a phase-change memory material having at least a high-resistance state and a detectably different low-resistance state and which can also be set by the set energy pulse from the high-resistance state to the low-resistance state An encryption method for storing and retrieving,
Wherein accumulation of at least one program energy pulse by at least one additional program energy pulse is detectably different from said high resistance state in said high resistance state, Storing information in the memory element by applying to the phase-change memory material at least one program memory pulse sufficient to modify the memory material so as to set the memory material in a low resistance state; And
To apply a further program energy pulse to the memory element until the memory element is detectably switched to its other low resistance state and the number of program energy pulses applied to cause the memory element to be in its low resistance state ≪ / RTI > wherein the step of counting comprises retrieving information stored in the memory element.
[2" claim-type="Currently amended] The method according to claim 1,
Wherein the energy is electrical energy.
[3" claim-type="Currently amended] The method according to claim 1,
Characterized in that the phase-change material comprises at least one element selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof Way.
[4" claim-type="Currently amended] The method of claim 3,
Wherein the phase-change material comprises at least one chalcogen element and at least one transition metal element.
[5" claim-type="Currently amended] 5. The method of claim 4,
Wherein the chalcogen element is selected from the group consisting of Te, Se and mixtures or alloys thereof.
[6" claim-type="Currently amended] 6. The method of claim 5,
Wherein the chalcogen element is a mixture of Te and Se.
[7" claim-type="Currently amended] The method according to claim 6,
Wherein the at least one transition metal element is selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof.
[8" claim-type="Currently amended] Resistance state and a low resistance state in order to change the connection ability in the nerve network, and also to change the connection state from the high resistance state to the low resistance state by the set energy pulse, A method of controlling an interconnecting element comprising a unit cell having a phase change material that can be set to a high resistance state,
Applying a reset energy pulse to the unit cell to reset the phase change material to its high resistance state; And
Applying a program energy pulse of a selected weight and duration to the unit cell based on a control strategy of the neural network, wherein at least some of the program energy pulses are applied to the memory material from the high- Resistance state in which the cumulative accumulation of at least some program energy pulses by at least one additional program energy pulse forms a first level of connection capability, and a second level different from the high- Is sufficient to deform the phase change material so as to set the phase change material in its low resistance state to form a coupling capability of the phase change material. ≪ Desc / Clms Page number 12 >
[9" claim-type="Currently amended] 9. The method of claim 8,
Wherein the energy is electrical energy.
[10" claim-type="Currently amended] 9. The method of claim 8,
Characterized in that the phase-change material comprises at least one element selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof Way.
[11" claim-type="Currently amended] 11. The method of claim 10,
Wherein the phase-change material comprises at least one chalcogen element and at least one transition metal element.
[12" claim-type="Currently amended] 12. The method of claim 11,
Wherein the chalcogen element is selected from the group consisting of Te, Se and mixtures or alloys thereof.
[13" claim-type="Currently amended] 13. The method of claim 12,
Wherein the chalcogen element is a mixture of Te and Se.
[14" claim-type="Currently amended] 14. The method of claim 13,
Wherein the at least one transition metal element is selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof.
[15" claim-type="Currently amended] A control apparatus for controlling a connection capability level between nodes in a node network of a neural network system,
A phase change which can be set from the high resistance state to the low resistance state by the set energy pulse and from the low resistance state to the high resistance state by the reset energy pulse at least in a high resistance state and a low resistance state, A unit cell having a material;
(a) applying an electrical energy to the phase change material to switch the phase change material between its high resistance state and its low resistance state, and (2) applying the phase change material when the phase change material is in its low resistance state First and second electrodes electrically connected to the phase change material to establish a signal conduction path through the material;
A control terminal electrically connected to the first electrode and a signal terminal;
A common control and signal terminal coupled to the second electrode;
The signal terminal being electrically connected to a first node of the node network and the common terminal being electrically connected to a second node of the node network for controlling a connection capability level between the first and second nodes, Terminals; And
And a neural network control system electrically connected to the control terminal and the common control and signal terminal for applying a weighted control pulse to the phase change material to switch the phase change material from its high resistance state to its low resistance state, Whereby the coupling capability level increases between the first and second nodes when the accumulation result of the control pulse exceeds the switching threshold level of the phase change material.
[16" claim-type="Currently amended] 16. The method of claim 15,
Wherein the energy is electrical energy.
[17" claim-type="Currently amended] 16. The method of claim 15,
Characterized in that the phase-change material comprises at least one element selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, O and mixtures or alloys thereof Way.
[18" claim-type="Currently amended] 18. The method of claim 17,
Wherein the phase-change material comprises at least one chalcogen element and at least one transition metal element.
[19" claim-type="Currently amended] 18. The method of claim 18,
Wherein the chalcogen element is selected from the group consisting of Te, Se and mixtures or alloys thereof.
[20" claim-type="Currently amended] 20. The method of claim 19,
Wherein the chalcogen element is a mixture of Te and Se.
[21" claim-type="Currently amended] 21. The method of claim 20,
Wherein the at least one transition metal element is selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof.

类似技术:

---

公开号 | 公开日 | 专利标题

---

TWI427633B|2014-02-21|One-transistor, one resistor, one capacitor phase change memory

---

US8110456B2|2012-02-07|Method for making a self aligning memory device

---

US8097487B2|2012-01-17|Method for making a phase change memory device with vacuum cell thermal isolation

---

US7935567B2|2011-05-03|Active material devices with containment layer

---

US5789758A|1998-08-04|Chalcogenide memory cell with a plurality of chalcogenide electrodes

---

US7910907B2|2011-03-22|Manufacturing method for pipe-shaped electrode phase change memory

---

US7700430B2|2010-04-20|Phase-changeable memory device and method of manufacturing the same

---

RU2214009C2|2003-10-10|Memory element with energy control mechanism

---

US7473574B2|2009-01-06|Memory element with improved contacts

---

US8238149B2|2012-08-07|Methods and apparatus for reducing defect bits in phase change memory

---

US7920415B2|2011-04-05|Memory cell device and programming methods

---

US7923285B2|2011-04-12|Method for forming self-aligned thermal isolation cell for a variable resistance memory array

---

EP1783844B1|2012-09-26|Phase change memory cell including multiple phase change material portions

---

US7956358B2|2011-06-07|I-shaped phase change memory cell with thermal isolation

---

US7879692B2|2011-02-01|Programmable resistive memory cell with self-forming gap

---

US7682868B2|2010-03-23|Method for making a keyhole opening during the manufacture of a memory cell

---

US7161167B2|2007-01-09|Lateral phase change memory

---

CN101197423B|2010-04-21|Method for making a self-converged memory material element for memory cell

---

US7932506B2|2011-04-26|Fully self-aligned pore-type memory cell having diode access device

---

US5335219A|1994-08-02|Homogeneous composition of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements

---

US7785920B2|2010-08-31|Method for making a pillar-type phase change memory element

---

US7732800B2|2010-06-08|Resistor random access memory cell with L-shaped electrode

---

US5596522A|1997-01-21|Homogeneous compositions of microcrystalline semiconductor material, semiconductor devices and directly overwritable memory elements fabricated therefrom, and arrays fabricated from the memory elements

---

EP1654735B1|2014-03-26|Multilayered phase change memory

---

US8319203B2|2012-11-27|Phase change material, a phase change random access memory device including the phase change material, and a semiconductor structure including the phase change material

同族专利:

---

公开号 | 公开日

---

CA2332867A1|2000-10-19|

---

EP1104578A4|2004-08-25|

---

JP2002541613A|2002-12-03|

---

MXPA00011876A|2002-10-31|

---

US6141241A|2000-10-31|

---

BR0006031A|2001-03-13|

---

EP1104578B1|2007-12-05|

---

KR100636086B1|2006-10-18|

---

WO2000062301A1|2000-10-19|

---

DE60037301T2|2008-11-27|

---

EP1104578A1|2001-06-06|

---

AU4081600A|2000-11-14|

---

DE60037301D1|2008-01-17|

---

RU2216054C2|2003-11-10|

引用文献:

---

公开号 | 申请日 | 公开日 | 申请人 | 专利标题

---

法律状态:
1999-04-12|Priority to US09/289,713

---

1999-04-12|Priority to US09/289,713

---

2000-04-12|Application filed by 마빈 에스. 시스킨드, 에너지 컨버젼 디바이시즈, 아이엔씨.

---

2001-06-25|Publication of KR20010052795A

---

2006-10-18|Application granted

---

2006-10-18|Publication of KR100636086B1

优先权:

---

申请号 | 申请日 | 专利标题

---

US09/289,713|1999-04-12|

---

US09/289,713|US6141241A|1998-06-23|1999-04-12|Universal memory element with systems employing same and apparatus and method for reading, writing and programming same|